Low Logic - HTB Challenge

Info

Category: Hardware
Difficulty: Easy
Key Topics: RTL (Resistor-Transistor Logic), NPN transistor circuits, NAND gate composition, combinational logic analysis

Abstract

Low Logic is a hardware challenge that presents an electronic circuit schematic and a CSV file containing 192 rows of 4-bit binary inputs. The task is to determine the Boolean logic function implemented by the circuit and apply it to each input row to reconstruct the flag one bit at a time. The circuit uses NPN transistors and resistors in an RTL (Resistor-Transistor Logic) configuration, implementing a composition of NAND gates that simplifies to (IN0 AND IN1) OR (IN2 AND IN3). This writeup covers both the circuit analysis approach and a brute-force alternative that tests candidate logic functions against the known flag prefix.

Circuit Analysis

RTL (Resistor-Transistor Logic) Fundamentals

The schematic (chip.jpg) shows a circuit built with NPN bipolar junction transistors (BJTs) and 1kOhm pull-up resistors. RTL was one of the earliest families of digital logic, predating TTL (Transistor-Transistor Logic) and CMOS. In RTL:

A high input (logic 1) at the base of an NPN transistor turns it on, pulling the collector toward ground (logic 0)
A low input (logic 0) keeps the transistor off, and the pull-up resistor holds the collector at Vcc (logic 1)

This means a single NPN transistor with a pull-up resistor acts as an inverter: high input produces low output, and vice versa.

Gate-Level Analysis

The circuit consists of three stages:

Stage 1 -- First NAND gate (IN0, IN1): Two NPN transistors have their collectors tied together to a single pull-up resistor. IN0 and IN1 drive the respective bases. When both transistors are on (both inputs high), the output is pulled low. Otherwise, the pull-up resistor holds the output high. This implements a NAND gate:

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Low Logic — HTB Challenge